In conventional memory redundancy, each memory includes one or more redundant features. For example, a memory with column redundancy will include a redundant column that may be used to replace the function of a defective column. Although such conventional redundancy techniques are quite effective to address memory defects, a modern system on a chip (SOC) will typically include numerous embedded memories.
If each embedded memory in an SOC implements conventional column redundancy, the SOC needs some way to store the defective column address (the column redundancy address) for any of the defective memories. A priori, one doesn't know whether a given memory has a defect so the SOC must then dedicate storage space for each memory with regard to its potential redundancy address. For example, if each memory has 128 columns then the corresponding redundancy addresses are each 7-bit words. If the SOC has 1000 embedded memories, it would then need a 7K bit memory to store the redundancy information. Such a relatively large memory demands excessive die area.
But it would virtually never be the case that each embedded memory has a defect. More typically, only a few (or less) of all the embedded memories in each SOC would be defective. For this reason, the fuses may be shared by all the embedded memories. For example, if the SOC is to have the ability to repair just one embedded memory, then the SOC would need just a few fuses as the resulting stored redundancy address would be shared by all the embedded memories.
Although fuse sharing thus advantageously offers considerable die savings over conventional dedicated redundancy addressing schemes, the embedded memories themselves become inefficient with regard to their die space usage. In particular, each embedded memory would include the circuitry for implementing redundancy yet at most a few of the embedded memories would ever use this circuitry. Indeed, as the number of embedded memories is increased, the vast majority of them would have their redundancy circuitry lie fallow and thus waste die space.
Accordingly, there is a need in the art for denser memory redundancy architectures and techniques.